1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory device and a method of manufacturing the same, and particularly relates to a structure of a nonvolatile semiconductor memory device, which can improve a coupling ratio between a floating gate electrode and a control gate electrode, as well as a method of manufacturing the same.
2. Description of the Background Art
A self-align STI (Shallow Trench Isolation) has been known as a technique for improving a density in a nonvolatile semiconductor memory device. The self-align STI is a technique for forming a trench in a self-aligned fashion using patterned doped polycrystalline silicon, which will form floating gate electrodes in a memory cell part.
FIG. 33 is a cross section of a conventional nonvolatile semiconductor memory device employing the self-align STI.
As shown in FIG. 33, the nonvolatile semiconductor memory device includes a peripheral circuit part and a memory cell part. A silicon oxide film 2 for element isolation is formed at a main surface of a semiconductor substrate 1 in the peripheral circuit part, and a trench 3 and a silicon oxide film 21 for element isolation are formed for at the main surface of semiconductor substrate 1 in the memory cell part.
Memory cell transistors are formed in the memory cell part. Each memory cell transistor has a floating gate electrode 8 formed on the main surface of semiconductor substrate 1 with a thermal oxide film 4 therebetween, an insulating film 9 and a control gate electrode 35.
Floating gate electrode 8 is formed of a doped polycrystalline silicon film 6, and control gate electrode 35 has a doped polycrystalline silicon film 10 and a WSi film 11. A silicon oxide film 12 is formed on control gate electrode 35.
MOS (Metal Oxide Semiconductor) transistors are formed in the peripheral circuit part. The MOS transistor has a gate electrode 13 formed on semiconductor substrate 1 with a thermal oxide film 5 therebetween. Gate electrode 13 has doped polycrystalline silicon film 10 and WSi film 11. Silicon oxide film 12 is formed on gate electrode 13.
The memory cell transistors and the MOS transistors described above are covered with an interlayer insulating film 14. Interlayer insulating film 14 has contact holes 15, in which tungsten plugs 16 are formed, respectively. An interconnection film 17 electrically connected to tungsten plug 16 is formed on interlayer insulating film 14.
A method of manufacturing the nonvolatile semiconductor memory device having the above structure will now be described with reference to FIGS. 34-38.
As shown in FIG. 34, silicon oxide film 2 is formed at the peripheral circuit part, and thermal oxide film 4 is formed on the main surface of semiconductor substrate 1. Doped polycrystalline silicon film 6 is formed on thermal oxide film 4, and is patterned.
Semiconductor substrate 1 masked with doped polycrystalline silicon film 6 is etched to form trench 3 at the memory cell part in a self-aligned fashion. Trench 3 is filled with silicon oxide film 21.
Then, insulating film 9 is deposited on doped polycrystalline silicon film 6, and photoresist 36 of a predetermined configuration is formed on insulating film 9. Etching is effected using photoresist 36 as a mask so that insulating film 9, doped polycrystalline silicon film 6 and thermal oxide film 4 on the peripheral circuit part are removed.
Then, as shown in FIG. 36, thermal oxide film 5 is formed on the peripheral circuit part, and doped polycrystalline silicon film 10, WSi film 11 and silicon oxide film 12 are deposited on thermal oxide film 5. Photoresist 37 of a predetermined configuration is formed on silicon oxide film 12, and silicon oxide film 12 masked with photoresist 37 is etched.
After removing photoresist 37, WSi film 11 and doped polycrystalline silicon film 10 masked with silicon oxide film 12 are etched. Thereby, control gate electrode 35 in the memory cell part and gate electrode 13 of the MOS transistor in the peripheral circuit part are formed as shown in FIG. 37.
Photoresist 38 covering the peripheral circuit part is formed, and etching is effected on insulating film 9 and doped polycrystalline silicon film 6 in the memory cell part using photoresist 38 as a mask. Thereby, floating gate electrode 8 is formed in the memory cell part.
Thereafter, interlayer insulating film 14 is deposited, and each contact hole 15 is formed in interlayer insulating film 14. Tungsten plug 16 is formed in contact hole 15, and interconnection film 17 is formed on interlayer insulating film 14. Through the steps described above, the nonvolatile semiconductor memory device shown in FIG. 33 is completed.
In the nonvolatile semiconductor memory device shown in FIG. 33, trench 3 for element isolation is formed by etching semiconductor substrate 1, which is masked with doped polycrystalline silicon film 6 forming floating gate electrode 8. Therefore, independent photolithography for forming trench 3 is not required, and therefore, it is not necessary to ensure, in the photolithography step, an overlapping margin and a margin required in view of variations in size. Therefore, the density in the nonvolatile semiconductor memory device can be improved.
However, due to the fact that the overlapping margin and the margin for variations in size are not required for the photolithography as described above, the surface area of floating gate electrode 8 decreases in the main surface direction of semiconductor substrate 1 as shown in FIG. 33.
This reduces the capacitance between control gate electrode 35 and floating gate electrode 8, and lowers the coupling ratio.
The invention has been made for overcoming the foregoing disadvantage, and it is an object of the invention to provide a nonvolatile semiconductor memory device, in which a coupling ratio between a control gate electrode and a floating gate electrode is improved.
A nonvolatile semiconductor memory device according to the invention includes a semiconductor substrate having a main surface; a floating gate electrode having a first conductive film formed on the main surface with a tunnel insulating film therebetween, and a second conductive film laid over the first conductive film and having a convexity; an insulating film covering the second conductive film; and a control gate electrode formed on the insulating film.
As described above, the second conductive film of the floating gate electrode is provided with the convexity, and the insulating film and the control gate electrode cover the convexity. Thereby, a capacitor can be formed between the convexity and the control gate electrode. This can increase the capacitance between the floating gate electrode and the control gate electrode.
Since the floating gate electrode has the multilayer structure formed of the conductive films, the following advantages can be achieved. The characteristics of the tunnel insulating film are significantly affected by a state of an interface between the semiconductor substrate and the tunnel insulating film as well as a state of an interface between the tunnel insulating film and the floating gate electrode. However, when forming the first conductive film, which will form the lower conductive film of the floating gate electrode, and thus when forming the interface between the tunnel insulating film and the floating gate electrode, an impurity concentration of the first conductive film, which is required for achieving a good state of the interface, may not match with an impurity concentration, which is electrically optimum for the floating gate electrode. Accordingly, the floating gate electrode is formed of, e.g., a multilayer structure having the first and second conductive films. Owing to this structure, the impurity concentration of the first conductive film can be kept at a value required for forming a good interface with respect to the tunnel insulating film, and further the impurity concentration of the second conductive film can be appropriately adjusted so that the impurity concentration of the floating gate electrode can likewise be set to an optimum value from the electrical viewpoint.
The convexity preferably includes an upward wall extending upward from a peripheral portion of the second conductive film. In this case, the insulating film and the control gate electrode cover the side surface of the upward wall.
Thereby, a capacitor can be formed between the upward wall of the floating gate electrode and the control gate electrode so that a capacitance between the floating gate electrode and the control gate electrode can be increased.
The nonvolatile semiconductor memory device has a trench for element isolation, and the trench is formed by etching the semiconductor substrate masked with the first conductive film.
As described above, the trench for element isolation is formed in a self-aligned fashion with respect to the first conductive film so that the density of the nonvolatile semiconductor memory device can be increased. However, this formation of the trench reduces a surface area of the first conductive film, which will form a portion of the floating gate electrode. In connection with this, the second conductive film, which is formed on the first conductive film and has the foregoing convexity, can increase the surface area of the floating gate electrode, and therefore can increase the capacitance between the floating gate electrode and the control gate electrode. Accordingly, the capacitance between the floating gate electrode and the control gate electrode can be increased while keeping a high density of the nonvolatile semiconductor memory device.
A method of manufacturing a nonvolatile semiconductor memory device according to the invention includes the following steps. A mask film including a first conductive film is formed on a main surface of a semiconductor substrate. Etching is effected on the semiconductor substrate masked with this mask film to form a trench for element isolation. A first insulating film covering the trench and the mask film is formed. The thickness of the first insulating film is reduced to expose the mask film. The thickness of the mask film is reduced to expose the first conductive film and to form a convexity projecting upward beyond an upper surface of the first conductive film at the first insulating film. A second conductive film covering the convexity is formed on the first conductive film. The second conductive film located on the convexity is removed to form an upward wall at the second conductive film. A second insulating film and a third conductive film both covering the upward wall are successively formed. The third conductive film, the second insulating film, the second conductive film and the first conductive film are patterned to form the floating gate electrode and the control gate electrode.
By etching the semiconductor substrate masked with the foregoing mask film, the trench can be formed in a self-aligned fashion with respect to the mask film (first conductive film). The thickness of the first conductive film covering the trench and the mask film is reduced to expose the mask film, whereby the first insulating film having an upper surface at the substantially same level as the upper surface of the mask film can be formed in the trench. Thereafter, the thickness of the mask film is reduced to expose the first conductive film so that the first insulating film having the convexity projecting upward beyond the upper surface of the first conductive film can be formed. The second conductive film covering the convexity is formed on the first conductive film, and the second conductive film located on the convexity is removed so that the upward wall extending upward along the side surface of the convexity can be formed at the second conductive film. The second insulating film and the third conductive film covering the upward wall are successively formed, and the third conductive film, the second insulating film, the second conductive film and the first conductive film are patterned to form the control gate electrode on the floating gate electrode with the second insulating film therebetween. In the above step, the upward wall can be formed at the second conductive film of the floating gate electrode so that a capacitor can be formed between the upward wall and the control gate electrode, and the capacitance between the floating gate electrode and the control gate electrode can be increased.
The mask film may be formed of a third insulating film layered on the first conductive film. In this case, the step of forming the mask film includes a step of forming the first conductive film on the main surface of the semiconductor substrate, and a step of forming the third insulating film on the first conductive film. The step of reducing the thickness of the mask film includes a step of exposing the first conductive film by removing the third insulating film.
Since the mask film has the third insulating film on the first conductive film as described above, the convexity can be formed at the first insulating film only by removing the third insulating film after reducing the thickness of the first insulating film. By adjusting the thickness of the third insulating film, the height of the convexity can be adjusted so that the height of the upward wall can be adjusted. By appropriately adjusting the thickness of the third insulating film, an intended capacitance can be provided between the floating gate electrode and the control gate electrode.
The step of forming the upward wall includes the steps of forming a coating film covering the second conductive film, reducing the thickness of the coating film to expose the surface of the second conductive film located on the convexity while leaving the coating film on the second conductive film located around the convexity, and removing the exposed second conductive film to form the upward wall.
Since the second conductive film extends above the convexity, irregularities are present at the surface of the second conductive film. In view of this, the coating film covering the second conductive film is formed, and the thickness of the coating film from its surface is reduced so that the surface of the second conductive film located on the convexity can be exposed while leaving the coating film on the second conductive film located around the convexity. By removing the exposed second conductive film, the second conductive film can be left along the side surface of the convexity, and the upward wall can be formed at the second conductive film.
The coating film includes photoresist. In this case, the step of forming the coating film includes a step of applying photoresist covering the second conductive film, and the step of reducing the thickness of the coating film includes a step of performing development after effecting exposure on the whole surface of the photoresist, and thereby exposing the surface of the second conductive film on the convexity while leaving the photoresist around the convexity. In this case, the upward wall can be formed at the second conductive film, similarly to the foregoing case.
The nonvolatile semiconductor memory device includes a peripheral circuit part and a memory cell part, and has a fourth insulating film for element isolation at the peripheral circuit part. The first insulating film is located within the memory cell part. In this case, the fourth insulating film may be formed before formation of the first insulating film, or may be formed in the same step as the first insulating film. The fourth insulating film may be formed by selectively oxidizing the semiconductor substrate, or may be formed within the trench for element isolation formed in the peripheral circuit part.
The fourth insulating film may be formed independently of the first insulating film, whereby the element isolating structures suitable to the peripheral circuit part and the memory cell part can be selected. By forming the fourth insulating film and the first insulating film in the same step, the process can be simple.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.